Low power sram thesis

Functionality[ edit ] Without a significant amount of memory, a computer would merely be able to perform fixed operations and immediately output the result. It would have to be reconfigured to change its behavior. This is acceptable for devices such as desk calculatorsdigital signal processorsand other specialized devices. Von Neumann machines differ in having a memory in which they store their operating instructions and data.

Low power sram thesis

The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal is above VCCP.

If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above VTH. The drive to increase both density, and to a lesser extent, performance, required denser designs. The minimization of DRAM cell area can produce a denser device which could be sold at a higher priceor a lower priced device with the same capacity.

Starting in the mids, the capacitor has been moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as stacked or folded plate capacitors; whereas those with capacitors buried beneath the substrate surface are referred to as trench capacitors.

In the s, manufacturers were sharply divided by the type of capacitor used by their DRAMs, and the relative cost and long-term scalability of both designs has been the subject of extensive debate. The majority of DRAMs, from major manufactures such as HynixMicron TechnologySamsung Electronics use the stacked capacitor structure, whereas smaller manufacturers such Nanya Technology use the trench capacitor structure Jacob, pp.

The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide ONO dielectric sandwiched in between two layers of polysilicon plates the top plate is shared by all DRAM cells in an ICand its shape can be a rectangle, a cylinder, or some other more complex shape.

There are two basic variations of the stacked capacitor, based on its location relative to the bitline—capacitor-over-bitline COB and capacitor-under-bitline CUB.

Development of a Low-Power SRAM Compiler

In a former variation, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter variation, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation.

The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline.

CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology Kenner, pp.

The trench capacitor is constructed by etching a deep hole into the silicon substrate. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top the capacitor is connected to the access transistor's drain terminal via a polysilicon strap Kenner, pp.

A trench capacitor's depth-to-width ratio in DRAMs of the mids can exceed Trench capacitors have numerous advantages.

Master Thesis Sram

Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance Jacob, pp.

Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area Kenner, pg. Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate.

The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise be degrading the logic transistors and their performance.

Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal Kenner, pg.

By the second-generation, the requirement to increase density by fitting more bits in a given area, or the requirement to reduce cost by fitting the same amount of bits in a smaller area, lead to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use the 3T1C cell for performance reasons Kenner, p.

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These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out non-destructive read. A second performance advantage relates to the 3T1C cell has separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation Jacob, p.

Proposed cell designs[ edit ] The one-transistor, zero-capacitor 1T DRAM cell has been a topic of research since the lates. In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor.

Low power sram thesis

Considered a nuisance in logic design, this floating body effect can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits, since they are constructed with the same silicon on insulator process technologies.

Array structures[ edit ] DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines. The physical layout of the DRAM cells in an array is typically designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their area.

This scheme permits comparison of DRAM size over different process technology generations, as DRAM cell area scales at linear or near-linear rates over. The horizontal wire, the wordline, is connected to the gate terminal of every access transistor in its row.

The vertical bitline is connected to the source terminal of the transistors in its a column.

Past Members – Gigascale Reliable Energy-Efficient Nanosystem (GREEN) Lab Massachusetts Institute of Technology. Massachusetts Institute of Technology Date Issued:
Master Thesis Low Power Sram Uncategorized A raisin in the sun writing assignment for those previously certified to teach in the state of Texas and a Master of Arts in Teaching M.

The lengths of the wordlines and bitlines are limited. The wordline length is limited by the desired performance of the array, since propagation time of the signal that must transverse the wordline is determined by the RC time constant.

The bitline length is limited by its capacitance which increases with lengthwhich must be kept within a range for proper sensing as DRAMs operate by sensing the charge of the capacitor released onto the bitline.

Low power sram thesis

Bitline length is also limited by the amount of operating current the DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.DESIGNING LOW POWER SRAM SYSTEM USING ENERGY COMPRESSION A Thesis Presented to The Academic Faculty by Prashant Jayaprakash Nair Bachelor of Engineering (with Distinction), University of Mumbai.

The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption during. This thesis focuses on the power dissipation during the Write operation in six-T CMOS SRAM as well as read operation also.

Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an important class of applications driving ultra-low-power SRAMs. This thesis analyzes the energy of an SRAM sub-array. Design and Analysis of Low-power SRAMs by Mohammad Sharifkhani A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Doctor of Philosophy in Electrical and Computer Engineering Waterloo, Ontario, Canada, c Mohammad Sharifkhani operation, low mobility and low speed.

To overcome some of these drawbacks of lateral OTFT, there is a search for convenient vertical structures using organic semiconductors. Computer data storage, often called storage or memory, is a technology consisting of computer components and recording media that are used to retain digital vetconnexx.com is a core function and fundamental component of computers.: 15–16 The central processing unit (CPU) of a computer is what manipulates data by performing computations.

In practice, almost all computers use a storage hierarchy.

Development of a Low-Power SRAM Compiler